This invention, pertains to phase locked loop circuits for extracting bit rate and frame rate clock signals in a high data rate communication link.
Phase Locked Loops (PLLs) are used in data communication link receivers to extract a clock signal from the incoming data stream. The essentially jitter-free clock signal is then used first to sample and then to regenerate the incoming data stream. This provides a regenerated data stream free from timing jitter introduced on the incoming data by bandwidth limitations of the transmission channel and by noise.
Phase Locked Loops consist usually of a phase detector for comparing the phase of the incoming bit stream with the phase of a locally generated clock, a low pass filter for smoothing the output signal of the phase detector, and a voltage controlled oscillator (VCO) for generating the local clock signal and being frequency controlled by the low pass filter output voltage.
In order to retime the incoming data correctly, with minimum requirements on the signal-to-noise ratio (SNR) of the incoming data, sampling of the incoming data by the local clock signal must occur as close as possible to the center of each consecutive bit time interval (1/bit rate) where the signal usually has its maximum amplitude. As shown in FIGS. 1a through 1c, a data stream as shown in FIG. 1a is transmitted over a communication link, with the received signal appearing as shown in FIG. 1b, due to noise and bandwidth limitations. This received signal from FIG. 1b is to be detected and used to provide a regenerated data stream as shown in FIG. 1c which accurately represents the desired data stream of FIG. 1a. As shown in FIG. 1b, received pulses tend to have their peaks near the center of the bit time interval in which they are transmitted. The phase locked loop, when in lock, guarantees a fixed phase relationship between the incoming bit stream and the locally generated clock. The actual position of the sampling instant relative to the bit time interval is, however, determined by the phase of the clock relative to the incoming data as enforced by the phase detector, and by the phase of the sampling instant relative to the clock which is determined by the operation of the sampling circuit.
In low bit rate communication links the duration of each bit time interval largely exceeds the parasitic propagation delays (or the variations thereof) of the digital circuitry. Consequently, if the sampling instant was set by design to the center of the bit time cell it will essentially stay there over temperature, supply voltage variations, and time. However, in gigabit rate links the propagation delays of the digital circuitry and their variations are very much comparable to the duration of the bit time interval, i.e. 1 nanosecond for a 1 Gigabit per second channel. It is therefore of utmost importance to eliminate the influence of such propagation delays on the position of the sampling instant relative to the bit time interval.
This can be achieved best by implementing the phase detector and the sampling circuit by two closely matched circuits of identical topology and rely on tracking of their propagation delays. Examples of such prior art PLL circuits for use in clock recovery systems in a high data rate communication link are found, for example, in Bentland et al., "Clock Recovery for a 5 Gbit/s Fibre Optic System", Electronics Letters, 24 June 1982, Vol. 18, No. 13, pp. 547-548, and C. Hogge, "A Self-Correcting Clock Recovery Circuit," IEEE Transactions on Electron Devices, Vol. ED-32, No. 12, December 1985. Bentland describes a circuit in which the transmitted data is grouped into consecutive frames, each consisting of 50 bits of Return to Zero (RZ) format. Bits are transmitted as pulses, with the first bit of each frame always present, as it is devoted only to marking the beginning of the frame and carries no other information. Before start of data communication (i.e. at link power up) a so-called training sequence is transmitted. The training sequence consists only of this reference pulse, with all other bits in the frame being set to zero (i.e. no pulse). On the receiving end, a phase locked loop generates a clock at the frame rate, i.e. at 1/50 of the bit rate, and this clock is phase locked to the incoming reference pulse stream. When lock has occurred, transmission of data is started. The presence of the reference pulse in each frame guarantees a continuing lock from which now both a frame rate as well as a bit rate clock can be derived. In the arrangement described by Bentland et al. the phase detector includes a delay line, with the position of the sampling point within a bit time interval being established by that delay. This requires undesirable adjustment of the delay line, and readjustment over time. Furthermore, the RZ format used in Bentland requires twice the link bandwidth for a given bit rate compared to the non return-to-zero (NRZ) format.